A conventional method of isolating semiconductor devices includes performing a LOCOS (local oxidation of silicon) process which achieves selective oxidation by using a nitride layer. More specifically, the LOCOS process thermally oxidizes a silicon wafer while using the nitride layer as a mask. Such a LOCOS process can reduce the stress of the oxide layer in a device and produce an oxide layer of good quality. However, the LOCOS process has limitations in manufacturing fine pattern semiconductor devices and causes bird's beak because the area of the device isolation region formed by the LOCOS process is relatively large.
To obviate these problems, a shallow trench isolation (hereinafter referred to as “STI”) process has been developed as an alternative technology. The STI method forms trenches within a silicon wafer and then fills them with an insulating material, thereby making device isolation structures of small size. Accordingly, the STI process is widely used to manufacture fine pattern devices.
Kim et al., U.S. Pat. No. 6,432,816, describes a method for fabricating a semiconductor device which can optimize an electrical property of a high integration device by preventing a device isolation film from being (a) damaged due to misalignment in a lithography process or (b) overetched during the etch process. In the above-mentioned patent, a protective film for protecting a device isolation film is formed on the device isolation film for use during a contact hole formation process.
Zheong et al., U.S. Pat. No. 6,417,054, describes a method for fabricating a self-aligned S/D CMOS device on an insulated layer by forming a trench along side the STI and filling the trench with oxide.
Lin et al., U.S. Pat. No. 6,309,948, describes a method for forming a semiconductor structure on an active area mesa with minimal loss of field oxide deposited in isolation trenches adjacent the mesa. In that method, the trench insulating material is protected by an etch barrier layer having at least a partial resistance to etchants used in further device processing steps.
Park et al., U.S. Pat. No. 6,107,143, describes a method for forming a trench isolation structure in an integrated circuit having high integration density. Park et al. use the difference in etching rate between (1) a sidewall-insulating layer formed along the sidewall and bottom of a trench and (2) a trench-insulating layer deposited in the trench to prevent the sidewall-insulating layer from being damaged during wet etching processes, thereby making an interface between the substrate, sidewall-insulating layer, and gate oxide more reliable.
FIG. 1 is a cross-sectional view illustrating a prior art semiconductor device having a device isolation structure. A conventional STI process comprises forming a trench by dry-etching a semiconductor substrate; curing damage due to the dry-etching; creating an oxide layer by thermally oxidizing the trench to enhance interface characteristics and edge rounding features of the active and device isolation regions; depositing a thick insulating layer all over the semiconductor substrate so as to completely fill the trench; and planarizing the semiconductor substrate using a chemical mechanical polishing process. Then, gate lines are formed on the resulting substrate.
However, the conventional STI process may cause several problems due to the difference in height between a field region 20 and a moat region 30. For example, polysilicon residues deposited on an area 1 between the field region 20 and the moat region 30 may cause leakage current. In addition, if a void 2 is created in the field region 20, the polysilicon residues infiltrate into the void to cause leakage current. On the other hand, if the field region 20 is lower in height than the moat region 30, a moat pit is created on the moat region 30 which is first opened during a polysilicon etching process. In the event of contact pattern misalignment, loss of the oxide 3 occurs on the field region 20 to thereby cause a leakage failure. Moreover, it is very difficult to control a critical dimension (hereinafter referred to as “CD”) during etching and patterning processes because of the difference in height between the field region and the moat region.